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1 LTC1401 complete so-8, 12-bit, 200ksps adc with shutdown the ltc ? 1401 is a complete 200ksps, 12-bit a/d con- verter that converts 0v to 2.048v unipolar input and draws only 15mw from a single 3v supply. this easy-to-use device comes complete with a 315ns sample-and-hold and a precision reference. maximum dc specifications include 1lsb inl, 1lsb dnl and 45ppm/ c full-scale drift over temperature. the LTC1401 has three power saving modes: nap and sleep, through the serial interface and shutdown by setting the shdn pin to zero. in nap mode, it consumes only 1.5mw of power and can wake up and convert immediately. in sleep (shutdown) mode, it consumes 19.5 m w (13.5 m w) of power typically. upon power-up from sleep or shutdown mode, a reference ready (refrdy) signal is available in the serial word to indicate that the reference has settled and the chip is ready to convert. the 3-wire serial port allows compact and efficient data transfer to a wide range of microprocessors, microcon- trollers and dsps. descriptio n u features n complete 12-bit adc with reference in so-8 n single supply 3v operation n sample rate: 200ksps n power dissipation: 15mw (typ) n 68db s/(n + d) and C 72db thd at 50khz n no missing codes over temperature n nap mode with instant wake-up: 1.5mw n sleep mode: 19.5 m w n shutdown mode: 13.5 m w n high impedance analog input n input range (0.5mv/lsb): 0v to 2.048v n internal reference can be overdriven externally n 3-wire interface to dsps and processors (spi and microwire tm compatible) single 3v supply, 200khz, 12-bit sampling a/d converter n low power and battery-operated systems n handheld or portable instruments n high speed data acquisition n digital signal processing n multiplexed data acquisition systems n telecommunication n digital radio n spectrum analysis applicatio n s u typical applicatio n u v cc a in v ref gnd shdn conv clk d out p1.4 p1.3 p1.2 LTC1401 mpu serial data link + 0.1 f 10 f + 0.1 f 10 f 1.20v analog input (0v to 2.048v) 4 3 2 1 5 6 7 8 3v 1401 ta01 sample rate (hz) 0.01 supply current (ma) 1 10 100 10 1k 1m LTC1401 ?ta02 0.1 0.01 0.001 0.1 1 100 10k 100k normal conversion nap mode between conversion shutdown mode between conversion sleep mode between conversion 3.2mhz clock t a = 25 c power consumption vs sample rate , ltc and lt are registered trademarks of linear technology corporation. microwire is a trademark of national semiconductor corporation.
2 LTC1401 absolute m axi m u m ratings w ww u (notes 1, 2) supply voltage (v cc ) ................................................. 7v analog input voltage (note 3) ..... C 0.3v to (v cc + 0.3v) digital input voltage (note 4) ....................C 0.3v to 12v digital output voltage .................. C 0.3v to (v cc + 0.3v) power dissipation .............................................. 300mw operating ambient temperature range LTC1401c................................................ 0 c to 70 c LTC1401i ............................................ C 40 c to 85 c operating junction temperature ......................... 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c package/order i n for m atio n w u u t jmax = 125 c, q ja = 130 c/ w top view v cc a in v ref gnd shdn conv clk d out s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 consult factory for pdip packages and military grade parts. LTC1401cs8 LTC1401is8 1401 1401i order part number s8 part marking symbol parameter conditions min typ max units v cc supply voltage 2.7 3.0 3.6 v i cc supply current f sample = 200ksps l 510 ma nap mode l 0.5 1.0 ma sleep mode l 6.5 15 m a shutdown mode l 4.5 10 m a p d power dissipation f sample = 200ksps l 15 30 mw nap mode l 1.5 3.0 mw sleep mode l 19.5 45 m w shutdown mode l 13.5 30 m w power require e ts w u (note 5) symbol parameter conditions min typ max units v in analog input range l 0 to 2.048 v i in analog input leakage current during conversions (hold mode) l 1 m a c in analog input capacitance between conversions (sample mode) 45 pf during conversions (hold mode) 5 pf put u i a a u log (note 5) i ter al refere ce characteristics u uu (note 5) parameter conditions min typ max units v ref output voltage i out = 0 1.180 1.200 1.220 v v ref output tempco i out = 0 l 10 45 ppm/ c v ref line regulation 2.7v v cc 3.6v 0.01 lsb/ v v ref load regulation 0 ? i out ? 1ma 2 lsb/ma v ref wake-up time from sleep or shutdown mode c vref = 10 m f3ms
3 LTC1401 parameter conditions min typ max units resolution (no missing codes) l 12 bits integral linearity error (note 7) l 1 lsb differential linearity error l 1 lsb offset error 6 lsb l 8 lsb full-scale error 15 lsb full-scale tempco i out(ref) = 0 l 10 45 ppm/ c cc hara terist ics co u verter with internal reference (note 5) symbol parameter conditions min typ max units s/(n + d) signal-to-noise 50khz input signal l 65 68 db plus distortion ratio 100khz input signal 65 db thd total harmonic distortion 50khz input signal l C72 C65 db up to 5th harmonic 100khz input signal C 66 db peak harmonic or 50khz input signal l C74 C65 db spurious noise 100khz input signal C 67 db imd intermodulation distortion f in1 = 49.853khz, f in2 = 53.076khz C 69 db full power bandwidth 2 mhz full linear bandwidth (s/(n + d) 3 68db) 50 khz accuracy ic dy u w a symbol parameter conditions min typ max units v ih high level input voltage v cc = 3.6v l 2.0 v v il low level input voltage v cc = 2.7v l 0.8 v i in digital input current v in = 0v to v cc l 10 m a c in digital input capacitance 5pf v oh high level output voltage v cc = 2.7v, i o = C 10 m a l 2.40 2.64 v v cc = 2.7v, i o = C 200 m a l 2.25 2.50 v v ol low level output voltage v cc = 2.7v, i o = 400 m a l 0.13 0.4 v i oz hi-z output leakage d out v out = 0v to v cc l 10 m a c oz hi-z output capacitance d out 15 pf i source output source current v out = 0 C 5 ma i sink output sink current v out = v cc 10 ma (note 5) digital i puts a n d outputs u u (note 5)
4 LTC1401 symbol parameter conditions min typ max units f sample(max) maximum sampling frequency l 200 khz t conv conversion time f clk = 3.2mhz l 4.1 m s t acq acquisition time 315 ns f clk clk frequency l 0.1 3.2 mhz t clk clk pulse width (note 6) l 60 ns t wk(nap) time to wake up from nap mode 350 ns t 1 clk pulse width to return to active mode l 60 ns t 2 conv - to clk - setup time l 100 ns t 3 conv - after leading clk - l 0ns t 4 conv pulse width (note 8) l 50 ns t 5 time from clk - to sample mode 80 ns t 6 aperture delay of sample-and-hold jitter < 50ps 45 ns t 7 minimum delay between conversion (note 6) l 350 550 ns t 8 delay time, clk - to d out valid c load = 20pf l 60 120 ns t 9 delay time, clk - to d out hi-z c load = 20pf l 60 120 ns t 10 time from previous data remains valid after clk - c load = 20pf l 15 50 ns (note 5) ti i g characteristics w u the l denotes specifications which apply over the full operating temperature range; all other limits and typicals apply to t a = 25 c. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to gnd. note 3: when these pin voltages are taken below gnd or above v cc , they will be clamped by internal diodes. this product can handle input currents greater than 40ma without latch-up if the pin is driven below gnd or above v cc . note 4: when these pin voltages are taken below gnd, they will be clamped by internal diodes. this product can handle input currents greater than 40ma without latch-up if the pin is driven below gnd. these pins are not clamped to v cc . note 5: v cc = 3v, f sample = 200khz, t r = t f = 5ns unless otherwise specified. note 6: guaranteed by design, not subject to test. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: the rising edge of conv starts a conversion. if conv returns low at a bit decision point during the conversion, it can create small errors. for best performance, ensure that conv returns low either within 120ns after the conversion starts (i.e., before the first bit decision) or after the 14 clock cycles. (figure 13 timing diagram).
5 LTC1401 typical perfor m a n ce characteristics u w code 0 1.0 dnl error (lsbs) 0.5 0 0.5 1.0 512 1024 1536 2048 LTC1401 ?tpc01 2560 3072 3584 4096 f sample = 200khz differential nonlinearity vs output code input frequency (khz) 10 0 signal/(noise + distortion)(db) 10 20 30 40 80 100 1000 LTC1401 ?tpc03 50 60 70 v in = 0db v in = 20db v in = 60db t a = 25 c f sample = 200khz s/(n + d) vs input frequency and amplitude acquisition time vs source impedance source resistance ( w ) 10 2500 t acq (ns) 3000 3500 4000 4500 100 1k 10k LTC1401 ?tpc06 2000 1500 500 0 1000 t a = 25 c signal-to-noise ratio (without harmonics) vs input frequency input frequency (khz) 10 0 signal-to-noise ratio (db) 10 20 30 40 80 100 1000 LTC1401 ?tpc04 50 60 70 t a = 25 c f sample = 200khz reference voltage vs load current load current (ma) ? 0.90 reference voltage (v) 0.95 1.05 1.10 1.15 1.40 1.25 ? ? ? 2 LTC1401 ?tpc07 1.00 1.30 1.35 1.20 ? ? ? 0 1 t a = 25 c temperature (?c) ?0 supply current (ma) 8 10 12 25 75 LTC1401 ?tpc09 6 4 ?5 0 50 100 125 2 0 v in = 3.6v v in = 3v v in = 2.7v f sample = 200khz supply current vs temperature integral nonlinearity vs output code peak harmonic or spurious noise vs input frequency input frequency (khz) 10 ?0 spurious-free dynamic range (db) ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 1000 LTC1401 ?tpc05 0 t a = 25 c f sample = 200khz power supply feedthrough vs ripple frequency code 0 1.0 inl error (lsbs) 0.5 0 0.5 1.0 512 1024 1536 2048 LTC1401 ?tpc02 2560 3072 3584 4096 f sample = 200khz ripple frequency (khz) 1 ?0 power supply feedthrough (db) ?0 ?0 ?0 ?0 10 100 1000 LTC1401 ?tpc08 ?0 ?0 ?0 100 ?0 0 f sample = 200khz f in = 49.853khz v cc (v ripple = 1mv)
6 LTC1401 pi n fu n ctio n s uuu v cc (pin 1): positive supply, 3v. bypass to gnd (10 m f tantalum in parallel with 0.1 m f ceramic). a in (pin 2): analog input. 0v to 2.048v. v ref (pin 3): 1.2v reference output. bypass to gnd (10 m f tantalum in parallel with 0.1 m f ceramic). gnd (pin 4): ground. gnd should be tied directly to an analog ground plane. d out (pin 5): the a/d conversion result is shifted out from this pin. LTC1401 ?bd01 12-bit capacitive dac comp successive approximation register/parallel to serial converter zeroing switch control logic 1.20v ref d out v cc conv clk v ref a in c sample 12 gnd shdn fu n ctio n al block diagra uu w LTC1401 ?tc01 d out d out 3k 3k c load c load hi-z to v oh v ol to v oh v oh to hi-z hi-z to v ol v oh to v ol v ol to hi-z 3v test circuits clk (pin 6): clock. this clock synchronizes the serial data transfer. a minimum clk pulse of 60ns signals the adc to wake up from nap or sleep mode. conv (pin 7): conversion start signal. this active high signal starts a conversion on its rising edge. keeping clk low and pulsing conv two/four times will put the adc into nap/sleep mode. shdn (pin 8): shutdown input. pull this pin low to put the adc in shutdown mode and save power (refrdy will go low). the device will draw 4.5 m a in this mode.
7 LTC1401 applicatio n s i n for m atio n wu u u conversion details the LTC1401 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit serial output based on a precision internal reference. the control logic provides an easy interface to microprocessors and dsps through serial 3-wire connections. a rising edge on the conv input starts a conversion. at the start of a conversion the successive approximation regis- ter (sar) is reset. once a conversion cycle has begun, it cannot be restarted. during conversion, the internal 12-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). referring to figure 1, the a in input connects to the sample-and-hold capacitor during the acquire phase and the comparator offset is nulled by the feedback switch. in this acquire phase, it typically takes 315ns for the sample-and-hold capacitor to acquire the analog signal. during the convert phase, the comparator feedback switch opens, putting the comparator into the compare mode. the input switches c sample to ground, injecting the analog input charge onto the summing junction. this input charge is successively compared with the binary-weighted charges supplied by the capacitive dac. bit decisions are made by the high speed comparator. at the end of a conversion, the dac output balances the a in input charge. the sar contents (a 12-bit data word) which represent the input voltage, are presented through the serial pin d out . dynamic performance the LTC1401 has excellent high speed sampling capabil- ity. fft (fast fourier transform) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algo- rithm, the adcs spectral content can be examined for frequencies outside the fundamental. figure 2a shows a typical LTC1401 fft plot. figure 1. a in input LTC1401 ?f01 sample d out c dac v dac dac a in c sample ? + comp s a r sample s1 hold signal-to-noise ratio the signal-to-noise plus distortion ratio [s/(n+d)] is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from dc to half the sampling frequency. figure 2a shows a typical spectral content with a 200khz sampling rate and a 50khz input. the dynamic perfor- mance is excellent for input frequencies up to the nyquist limit of 100khz as shown in figure 2b. frequency (khz) 02040507090 10 30 60 80 100 amplitude (db) LTC1401 ?f02a 0 10 20 30 40 50 60 70 ?0 90 100 110 120 f sample = 200khz f in = 49.853516khz sinad = 68.5db thd = ?2.4db v cc = 3v t a = 25 c figure 2a. LTC1401 nonaveraged, 4096 point fft plot with 50khz input frequency
8 LTC1401 applicatio n s i n for m atio n wu u u total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half of the sampling frequency. thd is expressed as: thd = 20log v2 2 + v3 2 + ...vn 2 v1 where v1 is the rms amplitude of the fundamental frequency and v2 through vn are the amplitudes of the second through nth harmonics. thd vs input frequency is shown in figure 4. the LTC1401 has good distortion performance up to the nyquist frequency and beyond. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer function can create distortion products at sum and differ- frequency (khz) 02040507090 10 30 60 80 100 amplitude (db) ltc1400 ?f02b 0 10 20 30 40 50 60 70 ?0 90 100 110 120 f sample = 200khz f in = 99.072266khz sinad = 65db thd = 66db v cc = 3v t a = 25 c input frequency (hz) 10k amplitude (db below the fundamental) 0 10 20 30 40 50 60 70 80 90 100 100k 1m LTC1401 ?f04 2nd harmonic thd 3rd harmonic t a = 25 c f sample = 200khz figure 4. distortion vs input frequency figure 2b. LTC1401 nonaveraged, 4096 point fft plot with 100khz input frequency effective number of bits the effective number of bits (enobs) is a measurement of the effective resolution of an adc and is directly related to the s/(n + d) by the equation: n sn d = + () /. . 176 602 where n is the effective number of bits of resolution and s/(n + d) is expressed in db. figure 3 shows enobs vs input frequency. figure 3. effective bits and signal-to-noise + distortion vs input frequency input frequency (hz) 10k effective number of bits signal/(noise + distortion) (db) 12 11 10 9 8 7 6 5 4 3 2 1 0 74 68 62 56 50 100k 1m LTC1401 ?f03 t a = 25 c f sample = 200khz
9 LTC1401 applicatio n s i n for m atio n wu u u driving the analog input the analog input of the LTC1401 is easy to drive. it draws only one small current spike while charging the sample- and-hold capacitor at the end of a conversion. during conversion, the analog input draws only a small leakage current. the only requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts. any op amp that settles in 315ns to small load current transients will allow maxi- mum speed operation. if a slower op amp is used, more settling time can be provided by increasing the time between conversions. suitable devices capable of driving the adcs a in input include the lt ? 1498 and the lt1630 op amps. the following list is a summary of the op amps that are suitable for driving the LTC1401, more detailed informa- tion is available in the linear technology databooks and the linearview tm cd-rom. lt1215/lt1216: dual and quad 23mhz, 50v/ m s single supply op amps. single 5v to 15v supplies, 6.6ma specifications, 90ns settling to 0.5lsb. lt1229/lt1230: dual and quad 100mhz current feedback amplifiers. 2v to 15v supplies, 6ma supply current each amplifier. low noise. good ac specs. lt1498/lt1499: dual or quad 10mhz, 6v/ m s, single 2.2v to 15v supplies, 1.7ma supply current per ampli- fier, input/output swings rail-to-rail. excellent ac and dc specs. lt1630: dual or quad 30mhz, 10v/ m s, single 2.7v to 15v supplies, 3.5ma supply current per amplifier, input/output swings rail-to-rail. good ac and dc specs. internal reference the LTC1401 has an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to 1.20v. it is internally connected to the dac and ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (fa + fb) and (fa C fb) while 3rd order imd terms includes (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). if the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order imd products can be expressed by the following formula. imd fa fb fa fb () = 20log amplitude at ( ) amplitude at fa figure 5 shows the imd performance at a 50khz input. figure 5. intermodulation distortion plot frequency (khz) 02040507090 10 30 60 80 100 amplitude (db) LTC1401 ?f05 0 10 20 30 40 50 60 70 ?0 90 100 110 120 f sample = 200khz fa = 49.853khz fb = 53.076khz t a = 25 c fa fb 3fa 2fb ?fa 2fa + fb 2fa ?fb 2fb + fa 2fa 3fb fa + fb 2fb fb ?fa peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full-scale input signal. full power and full linear bandwidth the full power bandwidth is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input signal. the full linear bandwidth is the input frequency at which the s/(n+d) has dropped to 68db (11 effective bits). linearview is a trademark of linear technology corporation.
10 LTC1401 applicatio n s i n for m atio n wu u u is available at pin 3 to provide up to 1ma current to an external load. for minimum code transition noise, the reference output should be decoupled with a capacitor to filter wideband noise from the reference (10uf tantalum in parallel with a 0.1uf ceramic is recommended). the v ref pin can be driven with a dac or other means to provide input span adjustment. the v ref pin must be driven to at least 1.25v to prevent conflict with the internal reference. the reference should not be driven to more than 3v. figure 6 shows an lt1360 op amp driving the reference pin. figure 7 shows a typical reference (lt1634-1.25) connected to the LTC1401. this will provide improved drift (equal to the maximum 25ppm/ c of the lt1634- 1.25) and a 2.1338v full scale. unipolar operation and adjustment figure 8 shows the ideal input/output characteristics for the LTC1401. the code transitions occur midway between successive integer lsb values (i.e., 0.5lsb, 1.5lsb, 2.5lsb, ... fs C 1.5lsb ). the output code is natural binary with 1lsb = 2.048/4096 = 0.5mv. figure 7. supplying a 2.5v reference voltage to the LTC1401 with the lt1634-1.25 LTC1401 ?f06 + v ref(out) 3 1.25v a in v ref gnd 10 f 3 input range 1.707 ?v ref(out) 3v LTC1401 lt1360 v cc LTC1401 ?f07 10 f 3 input range 1.707 ?v ref (= 2.1338v) lt1634-1.25 10v v in v out gnd 3v a in v ref gnd LTC1401 v cc figure 6. driving the v ref with the lt1360 op amp figure 8. LTC1401 unipolar transfer characteristics input voltage (v) 0v output code fs ?1lsb LTC1401 ?f08 111...111 111...110 111...101 111...100 000...000 000...001 000...010 000...011 1 lsb unipolar zero 1lsb = fs 4096 2.048 4096 = unipolar offset and full-scale error adjustments in applications where absolute accuracy is important, the offset and full-scale errors can be adjusted to zero. offset error must be adjusted before full-scale error. figure 9a shows the extra components required for full scale error adjustment. if both offset and full-scale adjustments are needed, the circuit in figure 9b can be used. for zero offset error, apply 0.25mv (i.e., 0.5lsb) at the input and adjust the offset trim until the LTC1401 output code flickers between 0000 0000 0000 and 0000 0000 0001. for zero full-scale error, apply an analog input of 2.04725v ( fs C 1.5lsb or last code transition ) at the input and adjust r5 until the LTC1401 output code flickers between 1111 1111 1110 and 1111 1111 1111.
11 LTC1401 applicatio n s i n for m atio n wu u u board layout and bypassing wire wrap boards are not recommended for high resolu- tion or high speed a/d converters. to obtain the best performance from the LTC1401, a printed circuit board is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital traces alongside an analog signal trace or underneath the adc. the analog input should be screened by gnd. high quality tantalum and ceramic bypass capacitors should be used at the v cc and v ref pins as shown in the typical application on the first page of this datasheet. for LTC1401 ?f09b + r2 10k r9 20 r4 100k r5 4.3k full-scale adjust r3 100k r6 400 r1 10k 10k analog input 0v to 2.048v a1 3v r8 10k offset adjust r7 100k 3v a in LTC1401 optimum performance, a 10 m f surface mount avx capaci- tor in parallel with a 0.1 m f ceramic is recommended for the v cc and v ref pins. the capacitors must be located as close to the pins as possible. the traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. input signal leads to a in and signal return leads from gnd (pin 4) should be kept as short as possible to minimize noise coupling. in applications where this is not possible, a shielded cable between the analog input signal and the adc is recommended. also, any potential difference in grounds between the analog signal and the adc appears as an error voltage in series with the analog input signal. attention should be paid to reducing the ground circuit impedance as much as possible. figure 10 shows the recommended system ground con- nections. all analog circuitry grounds should be termi- nated at the LTC1401 gnd pin. the ground return to the power supply from pin 4 should be low impedance for noise free operation. digital circuitry grounds must be connected to the digital supply common. figure 9a. LTC1401 full-scale adjust circuit LTC1401 ?f09a + r2 10k r3 10k r1 50 r4 100 full-scale adjust v in a1 LTC1401 a in gnd additional pins omitted for clarity 20lsb trim range figure 9b. LTC1401 offset and full-scale adjust circuit figure 10. power supply connection analog supply gnd 3v + LTC1401 v cc gnd digital supply gnd 3v + digital circuitry v cc gnd LTC1401 ?f10 power-down mode upon power up, the LTC1401 is initialized to the active state and is ready for conversion. however, the chip can be easily placed into nap or sleep mode by exercising the right combination of clk and conv signals. in nap mode, all power is off except the internal reference which remains active and provides 1.20v output voltage to the other
12 LTC1401 applicatio n s i n for m atio n wu u u circuitry. in this mode, the adc draws only 1.5mw of power instead of 15mw (for minimum power, the logic inputs must be within 500mv of the supply rails). the wake-up time from nap mode to active mode is 350ns. in sleep mode, power consumption is reduced to 19.5 m w by cutting off the supply to the comparator and reference. figure 11 illustrates power-down methods for the LTC1401. the chip enters nap mode by keeping the clk signal low and pulsing the conv signal twice. for sleep mode operation, conv signal should be pulsed four times while clk is kept low. nap and sleep modes are activated on the falling edge of the conv pulse. by pulling shdn low, the LTC1401 enters shutdown mode and power con- sumption drops to 13.5 m w. once shdn goes high, the LTC1401 returns to active mode or the LTC1401 returns to active mode by pulsing the clk signal if the device has entered nap/sleep mode. during the transistion from sleep mode to active mode, the v ref voltage ramp-up time is a function of its loading conditions. with a 10 m f bypass capacitor, the wake-up time from sleep mode is typically 3ms. a refrdy signal is activated once the reference has settled and is ready for an a/d conversion. this refrdy bit is sent to the d out pin as the first bit followed by the 12-bit data word (refer to figure 12). digital interface the digital interface requires only three digital lines. clk and conv are both inputs, and the d out output provides the conversion result in serial form. figures 12 and 13 show the digital timing waveform of the LTC1401 during the analog to digital conversion. the conv rising edge starts the conversion. once initiated, it can not be restarted until the conversion is completed. if the time from the conv signal to the clk rising edge is less than t 2 , the digital output will be delayed by one clock cycle. the digital output data is updated on the rising edge of the clk line. the digital output data consists of a refrdy bit followed by the valid 12-bit data word. d out data should be captured by the receiving system on the rising clk edge. data remains valid for a minimum time of t 10 after the rising clk edge to allow capture to occur. figure 11. nap mode and sleep mode waveforms clk conv nap sleep v ref t 1 t 1 refrdy note: nap and sleep are internal signals. refrdy appears as the first bit in the d out word. LTC1401 ?f11
13 LTC1401 applicatio n s i n for m atio n wu u u t 10 t 8 v ih v oh v ol d out clk t 9 v ih 90% 10% d out clk LTC1401 ?f13 figure 12. adc digital timing waveform figure 13. clk to d out delay clk conv internal s/h status d out t 7 t 3 12345678910111213 14 15 16 1 2 t 2 t 6 t 4 t 5 t 8 t acq sample sample hold hold refrdy bit + 12-bit data word hi-z hi-z t conv t sample lt1401 ?f12 refrdy d11 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d10 refrdy
14 LTC1401 typical applicatio n s u interface to the tms320c50s tdm serial port (frame sync is generated from tfsx) data from the LTC1401 loaded into the tms320c50s trcv register data stored in the tms320c50s memory (in right justified format) v cc a in v ref clk conv d out gnd tclkx tclkr tfsx tfsr tdr LTC1401 tms320c50 + 10 f 0.1 f unipolar input + 10 f 0.1 f 3v LTC1401 ?ta04a 1 8 2 3 4 6 7 5 shdn clk out 20mhz 5v qc clk a b c d clr ld p t 74hc161 2.5mhz external clock 1401 ta5b d0 x x 1401 ta4c d1 d2 d4 d5 d3 rdy x d11 d10 d9 d8 d7 d6 d2 d1 d0 1401 ta4d d3 d4 d6 d7 d5 0 0 0 rdy d11 d10 d9 d8 logic analyzer waveforms show 6.4 m s throughput rate (input voltage = 0.765v, output code = 0101 1111 1010 = 1530 10 )
15 LTC1401 typical applicatio n s u tms320c50 code for circuit this program demonstrates the LTC1401 interface to the tms320c50. frame sync pulse is generated from tfsx. data shift clock is derived from clkout. *initialization* .mmregs ; defines global symbolic names ;- - initialized data memory to zero .ds 0f00h ; initialize data to zero data0 .word 0 ; begin sample data location data1 .word 0 ; . data2 .word 0 ; location of data data3 .word 0 ; . data4 .word 0 ; . data5 .word 0 ; end sample data location ;- - set up the isr vector .ps 080ah ; serial ports interrupts rint : b receive ; 0a; xint : b transmit ; 0c; trnt : b trec ; 0e; txnt : b ttranx ; 10; ;- - setup the reset vector .ps 0a00h .entry start: *tms320c50 initialization* setc intm ; temporarily disable all interrupts ldp #0 ; set data page pointer to zero opl #0834h, pmst ; set up the pmst status and control register lacc #0 samm cwsr ; set software wait state to 0 samm pdwsr ; *configure serial port* splk #0028h, tspc ; set tdm serial port ; tdm = 0 stand alone mode ; dlb = 0 not loop back ; fo = 0 16 bits ; fsm = 1 burst mode ; mcm = 0 clkr is generated externally ; txm = 1 fsx as output pin ; put serial port into reset ; (xrst = rrst = 0) splk #00e8h, tspc ; take serial port out of reset ; (xrst = rrst = 1) splk #0ffffh, ifr ; clear all the pending interrupts *start serial communication* sacl tdxr ; generate frame sync pulse splk #040h, imr ; turn on trnt receiver interrupt clrc intm ; enable interrupt clrc sxm ; for unipolar input, set for right shift ; with no sign extension mar *ar7 ; load the auxiliary register pointer with seven lar ar7, #0f00h ; load the auxiliary register seven with #0f00h ; as the begin address for data storage wait: nop ; wait for a receive interrupt nop ; nop ; sacl tdxr ; !! regenerate the frame sync pulse b wait ; ; - - - - - - - end of main program - - - - - - - - - - ; *receiver interrupt service routine* trec: lamm trcv ; load the data received from LTC1401 sfr ; shift right two times sfr ; and #1fffh, 0 ; anded with #1fffh ; for converting the data to right ; justified format ; sacl *+, 0 ; write to data memory pointed by ar7 and ; increase the memory address by one lacc ar7 ; sub #0f05h,0 ; compare to end sample address #0f05h bcnd end_trcv, geq ; if the end sample address has exceeded jump to end_trcv ; splk #040h, imr ; else re-enable the trnt receive interrupt rete ; return to main program and enable interrupt *after obtained the data from LTC1401, program jump to end_trcv* end_trcv: splk #002h, imr ; enable int2 for program to halt clrc intm success: b success *fill the unused interrupt with rete, to avoid program get lost* ttranx: rete receive: rete transmit: rete int2: b halt ; halts the running cpu
16 LTC1401 typical applicatio n s u LTC1401 interface to the adsp2181s sport0 (frame sync is generated from rfs) data from the LTC1401 (normal mode) d0 x x d1 d2 d4 d5 d3 rdy x d11 d10 d9 d8 d7 d6 LTC1401 ?ta05c data stored in the adsp2181s memory (normal mode, slen = d) d2 d1 d0 d3 d4 d6 d7 d5 0 0 0 rdy d11 d10 d9 d8 LTC1401 ?ta05d 1401 ta04b logic analyzer waveforms show 4.8 m s throughput rate (input voltage = 1.604v, output code = 1100 1000 1000 = 3208 10 ) a in v cc v ref clk conv d out gnd sclko rfs dr0 LTC1401 adsp2181 unipolar input + 10 f 0.1 f + 10 f 3v 0.1 f 1 2 3 6 7 5 LTC1401 ?ta05a 8 shdn
17 LTC1401 typical applicatio n s u adsp2181 code for circuit this program demonstrates the LTC1401 interface to the adsp-2181. frame sync pulse is generated from rfs. data shift clock is internally generated. /*section 1: initialization*/ .module/ram/abs = 0 adspltc; /*define the program module*/ jump start; /*jump over interrupt vectors*/ nop; nop; nop; rti; rti; rti; rti; /*code vectors here upon irq2 int*/ rti; rti; rti; rti; /*code vectors here upon irql1 int*/ rti; rti; rti; rti; /*code vectors here upon irql0 int*/ rti; rti; rti; rti; /*code vectors here upon sport0 tx int*/ ax0 = rx0; /*section 5*/ dm (0x2000) = ax0; /*begin of sport0 receive interrupt*/ rti; /* */ /* */ /*end of sport0 receive interrupt*/ rti; rti; rti; rti; /*code vectors here upon /irqe int*/ rti; rti; rti; rti; /*code vectors here upon bdma interrupt*/ rti; rti; rti; rti; /*code vectors here upon sport1 tx (irq1) int*/ rti; rti; rti; rti; /*code vectors here upon sport1 rx (irq0) int*/ rti; rti; rti; rti; /*code vectors here upon timer int*/ rti; rti; rti; rti; /*code vectors here upon power down int*/ /*section 2: configure sport0*/ start: /*to configure sport0 control reg*/ /*sport0 address = 0x3ff6*/ /*rfs is used for frame sync generation*/ /*rfs is internal, tfs is not used*/ /*bit 0-3 = slen*/ /*f = 15 = 1111*/ /*e = 14 = 1110*/ /*d = 13 = 1101*/ /*bit 4,5 data type right justified zero filled msb*/ /*bit 6 invrfs = 0*/ /*bit 7 invtfs = 0*/ /*bit 8 irfs=1 receive internal frame sync*/ /*bit 9,10,11 are for tfs (dont care)*/ /*bit 12 rfsw=0 receive is normal mode*/ /*bit 13 rtfs=1 receive is framed mode*/ /*bit 14 isclk = 1 clock is internal*/ /*bit 15 multichannel mode = 0*/ ax0 = 0x6f0d; dm (0x3ff6) =ax0; /*section 3: configure clkdiv and rfsdiv, setup interrupts*/ /*to configure clkdiv reg*/ ax0= 4; dm(0x3ff5) =ax0; /*set the serial clock divide modulus reg sclkdiv*/ /*the input clock frequency = 16.67mhz*/ /*clkout frequency = 2x = 33mhz*/ /*sclk= 1/2*clkout*1/(sclkdiv+1)*/ /*for sclkdiv = 4, sclk = 33/10 = 3.3mhz*/ /*to configure rfsdiv*/ ax0 = 15; /*set the rfsdiv reg = 15*/ /*=> the frame sync pulse for every 16 sclk*/ /*if frame sync pulse in every 15 sclk, ax0=14*/ dm(0x3ff4) =ax0; /*to setup interrupt*/ ifc= 0x0066; /*clear any extraneous sport interrupts*/ icntl= 0; /*irqxb = level sensitivity*/ /*disable nesting interrupt*/ imask= 0x0020; /*bit 0 = timer int = 0*/ /*bit 1 = sport1 or irq0b int = 0*/ /*bit 2 = sport1 or irq1b int = 0*/ /*bit 3 = bdma int = 0*/ /*bit 4 = irqeb int = 0*/ /*bit 5 = sport0 receive int = 1*/ /*bit 6 = sport0 transmit int = 0*/ /*bit 7 = irq2b int = 0*/ /*enable sport0 receive interrupt*/ /*section 4: configure system control register and start communication*/ /*to configure system control reg*/ ax0 = dm(0x3fff); /*read the system control reg*/ ay0 = 0xfff0; ar = ax0 and ay0; /*set wait state to zero*/ ay0 = 0x1000; ar = ar or ay0; /*bit 12 = 1, enable sport0*/ dm(0x3fff) = ar; /*frame sync pulse regenerated automatically*/ cntr = 5000; do waitloop until ce; nop; nop; nop; nop; nop; nop; waitloop: nop; rts; .endmod;
18 LTC1401 typical applicatio n s u quick look circuit for converting data to parallel format 1 8 LTC1401 conv clk d out gnd analog input (0v to 2.048v) 12 11 14 13 15 1 2 3 4 5 6 7 9 qa qb qc qd qe qf qg qh qh' d0 d1 d2 d3 d4 d5 d6 d7 rck srck ser g 0.1 f 10 f + 10 f 0.1 f 1.20v reference output + srclr 74hc595 12 11 14 13 15 1 2 3 4 5 6 7 9 qa qb qc qd qe qf qg qh qh' d8 d9 d10 d11 refrdy rck srck ser g srclr 74hc595 clk conv 5v 3-wire serial interface link 3v LTC1401 ?ta03 3 v ref 4 2 v cc shdn a in 7 6 5
19 LTC1401 dimensions in inches (millimeters) unless otherwise noted. package descriptio n u s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 0996 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20 LTC1401 ? linear technology corporation 1998 1401f lt/tp 0598 4k ? printed in usa typical applicatio n s u interface to the tms320c50s tdm serial port (frame sync is generated from tfsx) related parts 12-bit parallel output adcs part number description comments ltc1273/ltc1275/ltc1276 complete 5v sampling 12-bit adcs with 70db sinad at niquist lower power and cost effective for f sample 300ksps ltc1274/ltc1277 low power 12-bit adcs with nap and sleep mode shutdown lowest power (10mw) f sample 100ksps ltc1278/ltc1279 high speed sampling 12-bit adcs with shutdown cost effective 12-bit adcs with convert start input best for 300ksps < f sample 600ksps ltc1282 complete 3v 12-bit adcs with 12mw power dissipation fully specified for 3v powered applications, f sample 140ksps ltc1409 low power 12-bit, 800ksps sampling adc best dynamic performance f sample 800ksps, 80mw dissipation ltc1410 12-bit, 1.25msps sampling adc with shutdown best dynamic performance, thd = C 84db and sinad = 71db at nyquist 12-bit serial output adcs part number v cc sample rate power dissipation description ltc1285/ltc1288 3v 7.5/6.6ksps 0.48mw 3v, one or two input, micropower, so-8 ltc1286/ltc1298 5v 12.5/11.1ksps 1.25mv one or two input, micropower, so-8 ltc1290 5/ 5v 50ksps 30mw 8 input, full-duplex serial i/o ltc1296 5/ 5v 46.5ksps 30mw 8 input, half-duplex serial i/o, power shutdown output ltc1400 5/ 5v 400ksps 75mw complete 12-bit, 400ksps, so-8 adc with shutdown ltc1404 5/ 5v 600ksps 75mw complete 12-bit, 600ksps, so-8 adc with shutdown v cc a in v ref clk conv d out gnd tclkx tclkr tfsx tfsr tdr LTC1401 tms320c50 + 10 f 0.1 f unipolar input + 10 f 0.1 f 3v LTC1401 ?ta04a 1 8 2 3 4 6 7 5 shdn clk out 20mhz 5v qc clk a b c d clr ld p t 74hc161 2.5mhz external clock LTC1401 interface to the adsp2181s sport0 (frame sync is generated from rfs) a in v cc v ref clk conv d out gnd sclko rfs dr0 LTC1401 adsp2181 unipolar input + 10 f 0.1 f + 10 f 3v 0.1 f 1 2 3 6 7 5 LTC1401 ?ta05a 8 shdn linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com

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